Larvicides target mosquito larvae, representing a major advantage over adult control, in which changes in biting and resting behaviors can lead adult mosquitoes to evade control activities. In addition, microbial larvicides from bacteria Bti and Bs have different modes of action than pyrethroid insecticides; therefore, microbial larvicides do not aggravate pyrethroid resistance. Microbial larvicides are also considered safe for non-target organisms and human health. Furthermore, larval control does not conflict with but rather complements the front-line ITN and IRS malaria control programs. Larval control may now be timelier than ever, since pyrethroid resistance and outdoor malaria transmission are increasing in Africa. However, there are some potential limitations of larviciding as it is practiced today. Although there are three formulations of long-lasting larvicide available for use in different habitat types , the classification of habitats is primarily based on the longevity of the aquatic period and productivity of the habitat. The longevity of the aquatic period may be visually identified; however, the productivity of a habitat may change over time. Canopy cover in the habitat, such as grasses in the water, may affect the spread of Bti/Bs [Zhou, personal observations]. Furthermore, heavy rainfall may wash away Bti/Bs and create new habitat; therefore, additional Bti/Bs may need to be applied at an unplanned time after the rain. There are also limitations for the design. The incidence of clinical malaria is essential for the evaluation of intervention success. However, as pointed out by previous studies, crude health facility records are not always a reliable source of such information and may in fact under estimate the true clinical incidence rate. However, as long as clinical malaria was diagnosed the same way across all health care facilities,vertical farming pros and cons comparison between intervention and control groups is justified. EIR is a good measure of reduction in transmission since larval control reduces overall vector population density and EIR is measured based on vector population density.
Additional indicators, such as clinical incidence through active case surveillance, can be a more accurate estimate of incidence, and parasite prevalence through cross-sectional surveillance may be helpful. However, as per restrictions imposed by the funding policy, direct measures of human subjects are restricted. Despite very high bed net coverage, malaria incidence in many African sites is resurging after a short-time reduction when ITN and IRS scale-up was initially rolled out. This malaria resurgence is caused primarily by increases in insecticide resistance and outdoor transmission. New cost-effective methods beyond bed nets and IRS are urgently needed. Long-lasting microbial larviciding represents a promising new tool that can target both indoor and outdoor transmission and alleviate the problem of pyrethroid resistance. Comprehensive evaluation of potentially cost-effective LLML will provide critically needed data for determining whether LLML can be used as a supplemental malaria control tool to further reduce malaria incidence in Africa.Data centers are managing increasing demands in data volume and processing power. High performance connectivity between servers and storage within a rack and across multiples racks are necessary to provide sufficient data bandwidth. The type and length of the data connection depends on signaling technology and cost. Passive copper interconnects are the most viable approach of short distances up to 10∼12 meters at 10Gbps per wire pair. Fig. 1.1 shows a data center with an arrangement of racks, where the 12m shaded area shows the reach of passive copper cables. Beyond the 12m range, racks of switches need to be inserted to extend the connectivity, regenerate and repeat the data. This represents an overhead in power and cost to the data center designer. Active copper cables with embedded amplification circuitry can extend the passive copper cable reach, but are typically limited to less than 20m.
For longer lengths of exceeding a kilometer, optical fibers are the only option that offers sufficient performance but at substantial cost. Lengths of <150 meters are an intermediate distance that can be particularly suitable for multiple 10Gbps lanes within a data center to connect across a row of racks to core switches at the end of a row. This work explores an active cable approach based on a source synchronous architecture to extend the range for copper cables to >100 meters for per-pair data rate >10Gbps. Unlike 10GBASE-T signaling, the approach does not require complex symbols at a lower symbol rate across multiple signaling pairs and dissipates ∼4W per port. The proposed link uses low power and area repeaters powered through the cable that can potentially be embedded in the cable. Source synchronous links have been proposed and used in server systems for multi-lane high speed serial link applications such as connecting CPU to CPU, to memory, or to bridge chips due to their inherent tracking of correlated jitter. A source synchronous receiver can track jitter in the received data by using a clock that is forwarded from the same transmitter that sends the data. The transmitted clock undergoes almost identical noisy environment as the transmitted data, particularly with similar supply and substrate noise. As a result, data jitter is transparent to the receiver by using the received clock to re-time it. Hence, only static and slowly varying phase offset need to be corrected for using slow phase compensation loops. This approach mitigates the need for fast and power hungry CDRs that are used traditionally in embedded clock link design. In addition, the power and hardware needed for the extra clock channel is usually simpler than the circuits for data transceivers and amortized by using multiple data lanes. In practice, the correlation between the timing of the clock and the data is weakened when a delay difference between the clock and the data path is present. Excessive delaycan cause correlated jitter in the clock path and data path to add instead of subtract and thus deteriorates the jitter tolerance.
For that reason, delay mismatch between clock and data path are minimized. At the same time, uncorrelated noise need to be filtered especially for high frequencies near and above the data bandwidth. In literature, different clock forwarding techniques have been proposed to deal with the aforementioned problem. In a clean-up PLL is used in the clock path at the receiver side. The PLL has sufficient bandwidth to track correlated jitter in the data path, and cut-off high frequency jitter. Another approach uses a DLL. The all-pass characteristic provides jitter correlation between clock and data paths, and jitter does not accumulate within the DLL. Delay has to be matched carefully between the clock and data paths to avoid jitter amplification. Similar to a DLL, an MDLL is used in to multiply a lower frequency forwarded clock to one at half the data rate. As an alternative to an MDLL, an injection locked oscillator is used to filter out uncorrelated jitter. Recently, the ILO has drawn more attention in source synchronous links because of its simplicity and wider bandwidth compared to a PLL which in turn enables it to track a wide range of correlated jitter. Fig. 1.2 shows a block diagram of the proposed clock-forwarded cable-link architecture. The forwarded clock tracks the jitter of the data across a wide frequency range. At each repeater stage, the data signal is equalized, amplified,air racking and retimed by the forwarded clock before being transmitted. Since, the relative jitter between the clock and the data is reset when the signal is retimed, the data repeating distance is defined mainly by the distance that can be easily transmitted with little power cost. Clock is transmitted on a separate channel without equalization. The clock frequency is a system variable that is determined using the model presented in the next section. A CMU multiplies the clock frequency from the forwarded frequency to half the data rate in each repeater. The clock and data repeating distance are not constrained to be the same. As seen from Fig. 1.2, clock can be tapped at each data repeating stage for frequency multiplication and retiming, and amplified/buffered at each clock repeating stage. The critical challenge in a repeating a source-synchronous system is the accumulation of clock jitter. Hence, maintaining a clean clock is the focus of this thesis. Determining a fine balance in forward clock frequency is crucial in defining jitter performance of the cable link. Frequency beyond the cable bandwidth results in large attenuation of clock amplitude creating more noise and jitter accumulation along clock repeater. On the other hand, frequency well below the cable bandwidth will increase jitter accumulation time and will degrade jitter performance inside the clock multiplier.
The trade-off between low frequency clock jitter accumulation in the Clock Multiplication Unit and the high frequency jitter accumulation along the clock repeaters is one of the defining aspects of optimizing the active copper link. We propose an FIR jitter filtering technique that requires little area and power cost, but drastically reduces clock jitters accumulation. We also utilize a programmable PLL/MDLL clock multiplication unit to verify and compare different clock configurations along the repeated link. The dissertation is composed of seven chapters. Chapter 2 gives the necessary overview on the most common repeater designs used nowadays and common clock multiplication topolgoies. The chapter then presents background on most commonly used CMU architectures. An overview on jitter metrics is also provided in this chapter, together with analysis of jitter on basic building blocks; an inverter and a differential pair. In Chapter 3, we propose a fast and accurate model for modeling clock forwarded repeater links. We use the model to evaluate link design space and different system parameters. In Chapter 4, system and implementation details are presented. We present a configurable and high speed clock multiplication PLL/MDLL in this chapter that is more than twice the speed of MDLLs published in literature. The experimental results are shown in Chapter 5. Chapter 6 concludes the work, list the contributions and offers some ideas for future work.Two repeater architectures are commonly used: referenceless CDR-based repeater and fully synchronized repeater. Fig. 2.1 shows a block diagram of a referenceless CDR, where phase acquisition occurs by connecting the VCO to a CDR loop where its frequency, and thus phase, is locked to the incoming data stream. The lock range is usually narrow and a frequency detector is often used to bring the VCO center frequency close to the data rate. This architecture poses the traditional trade-off between jitter filtering and the jitter tracking requirements by the CDR loop. Nevertheless, it should have wide enough bandwidth so that recovered clock can tolerate and track data jitter to minimize bit error rate due to timing wander and low-frequency noise. Jitter peaking is another system parameter that presents challenge in the design of referenceless CDR repeater. Peaking in the transfer function of the CDR due to phase margin less than 600 causes jitter amplification at the peaking frequency. Cascading multiple repeaters can cause excessive jitter accumulation at the peaking frequency which deteriorates the overall system performance and its tolerance to jitter. In addition, design of a frequency detector that covers a very wide range requires additional specialized circuits. An alternate architecture is the fully-synchronized repeater shown in Fig. 2.1. The architecture is similar except that a FIFO buffer is used to decouple the jitter filtering from the jitter tracking requirements. The CDR can thus have wide bandwidth for better tracking, and a clean oscillator/PLL is used at the output to read data from a FIFO buffer. The FIFO buffer handles any timing wander or frequency mismatch in the system. A driver, synchronized to the clean clock, transmits the data to the next repeater. This repeater is more robust but comes at the expense of more power and area due to the FIFO and clean oscillator/PLL.PLLs are commonly used to provide accurate timing signals for both transmit and receive sides of a high-speed link. In its simplest form, a PLL is a 2nd order feedback system that generates a clock signal whose output phase is aligned with respect to the phase of an input reference clock. Since phase is the integration of frequency, once the phases are aligned, both phase and frequency are locked. This alignment is achieved by comparing the phase of the output clock with the phase of the reference. Any resulting difference in phase, the phase error, feeds into a block that filters this error and generates a control signal, typically a voltage.